Instructors: Frank Crow and Pat Hanrahan

Reading List

Background

Advanced Raster Graphics Architectures, S. Molnar and H. Fuchs, Chapter 18, from Foley, van Dam, Feiner and Hughes.

pp. 521-525, Computer Architectures: A Quantitative Approach, J. Hennessy, D. Patterson.

Framebuffer memory design

J. Kajiya, I. Sutherland, Cheadle, A Random-Access Video Frame Buffer, Proc. Conference on Computer Graphics, Pattern Recognition and Data Structure, 1975.

R. Sproull, Frame Buffer Display Architectures, Annual Review of Computer Science, 1986.

M. Whitton, Memory Design for Raster Graphics Displays, IEEE CG&A, March 1984.

F. Crow, M. Howard, A Frame Buffer System with Enhanced Functionality, Computer Graphics, 15(3), pp. 63-70, 1981.

M. Wilkes et al, The Rainbow Workstation, Computer Journal, 27(2), 1984.

Pinkham, Novak, and Guttag, Video RAM Excels at Fast Graphics, Electronic Design, v. 13, no. 7 Aug. 18, 1983

M. Deering, S. Schlapp, M. Lavelle, FBRAM: A New Form of Memory Optimized for 3D Graphics, Computer Graphics, pp. 167-174, 1994.

Rasterization Architectures

N. Gharachlorloo, S. Gupta, R. Sproull, I. Sutherland, A Characterization of Ten Rasterization Techniques, Computer Graphics, 23(3), 1989.

Demetrescu, High Speed Image Rasterization Using Scan Line Access Memories, Proceedings of the 1985 Chapel Hill Conference on VLSI, Computer Science Press.

Parallelism

F. Crow, Parallel Computing for Graphics.

S. Molnar, M. Cox, D. Ellsworth, H. Fuchs, A Sorting Classification for Parallel Rendering, IEEE CG&A, 14(4), pp. 23-31, 1994.

F. Crow, G. Demos, K. Sims, 3D Image Synthesis on the Connection Machine, Intl. Journal of High Speed Computing 1(2), June 1989, World Scientific, Singapore.

T. Crockett, T. Orloff, A Parallel Rendering Algorithm for MIMD Architectures, Proc. Parallel Rendering Symposium, ACM Press, NY, pp. 35-42, 1993.

T. Crockett, T. Orloff, Parallel Polygon Rendering for Message-Passing Architectures, IEEE Parallel and Distributed Technology, 2(2), pp. 17-29, 1994.

D. Ellsworth, A New Algorithm for Interactive Graphics on Multicomputers, IEEE CG&A, 14(4), pp. 33-40, 1994.

S. Whitman, Dynamic Load Balancing for Parallel Polygon Rendering, IEEE CG&A, 14(4), pp. 41-48, 1994.

Case Studies

Schumaker, (CT-5) A New Visual System Architecture, 2nd ... Training Equipment Conference, 1980

H. Fuchs, J. Poulton, Pixel-Planes: A VLSI-Oriented Design for a Raster Graphics Engine, VLSI Design, 2(3), pp. 20-28, 1981.

K. Akeley, T. Jermoluk, High Performance Polygon Rendering, Computer Graphics, 22(4), pp. 239-246, 1988.

M. Deering, S. Winner, B. Schediwy, C. Duffy, N. Hunt, The Triangle Processor and Normal Vector Shader: A VLSI System for High Performance Graphics, Computer Graphics, 22(4), pp. 21-30, 1988.

B. Apgar, B. Bersack, A. Mammen, A Display System for the Stellar GS1000, Computer Graphics, 22(4), pp. 239-246, 1988.

H. Fuchs, J. Poulton, J. Eyles, T. Greer, J. Goldfeather, D. Ellsworth, S. Molar, G. Turk, B. Tebbs, L. Israel, Pixel Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor Enhanced Memories, Computer Graphics, 23(3), pp. 79-88. 1989.

M. Potmesil and E. Hoffert, The Pixel Machine, Computer Graphics, 23(3), pp. 69-78, 1989.

D. Kirk and D. Voorhies, The Rendering Architrecture of the DN10000VS, Computer Graphics, 24(4), pp. 299-308, 1990.

M. Kelley, S. Winner, K. Gould, Scalable Hardware Render Accelerator Using A Modified Scanline Algorithm, Computer Graphics 26(2), pp. 241-248, 1992.

S. Molnar, J. Eyles, J. Poulton, PixelFlow: High-Speed Rendering Using Image Composition, Computer Graphics, 26(2), pp. 231-240, 1992.

C. B. Harrell and F. Fouladi, Graphics Rendering Architecture for a High Performance Desktop Workstation, Computer Graphics, pp. 93-100, 1993.

M. Deering, S. R. Nelson, Leo: A System for Cost Effective 3D graphics, Computer Graphics, pp. 101-108, 1993.

K. Akeley, Reality Engine Graphics, Computer Graphics, pp. 109-116, 1993.

E&S Freedom 3000S.

Denali Technical Overview, Version 1.0, Kubota Pacific Computer, 1993.

GLINT Chip

Other Papers and Topics

Meyer and Sutherland, On the Design of Display Processors, CACM, 11(6), 1968.

P. Haeberli and K. Akeley, The Accumulation Buffer, Computer Graphics 24(4), pp. 309-318, 1990.

J. C. Dunwoody and M. Linton, Tracing Interactive 3D Graphics Programs, Computer Graphics (Proc. Symp. Interactive 3D Graphics), 24(2), pp. 155-163, 1990.

A. Goris, B. Frederickson, H. Baeverstad, A Configurable Pixel Cache for Fast Image Generation, IEEE CG&A, 7(3), pp. 24-32, 1987.

M. Regan and R. Pose, Priority Rendering with a VR Address Recalculation Pipeline, Computer Graphics, pp. 155-162, 1994.

G. Bishop, H. Fuchs, L. McMillan, E. Scher Zagier, Frameless Rendering: Double Buffering Considered Harmful, Computer Graphics, pp. 175-176, 1994.